scope:

This drawing forms a part of a one part - one part number documentation system (see 6.6 herein). Two product assurance classes consisting of military high reliability (device classes Q and M) and space application (device class V), and a choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). Device class M microcircuits represent non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883, "Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices". When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.

The PIN shall be as shown in the following example:

Device class M RHA marked devices shall meet the MIL-I-38535 appendix A specified RHA levels and shall be marked with the appropriate RHA designator. Device classes Q and V RHA marked devices shall meet the MIL-I-38535 specified RHA levels and shall be marked with the appropyiate RHA designator. A dash (-) indicates a non-RHA device.

The device type(s) shall identify the circuit function as follows:

Device type Generic number Circuit function 01 68332 1/ 32-bit integrated microcontroller

The device class designator shall be a single letter identifying the product assurance level as follows:

Device class Device requirements documentation M Vendor self-certification to the requirements for non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883 Q or V Certification and qualification to MIL-I-38535

The case outline(s) shall be as designated in MIL-STD-1835 and as follows:

Outline letter Descriptive designator Terminals Package style Z CMGA5-P132 132 Pin grid array Y See figure 1 132 Gullwing leaded chip carrier

The lead finish shall be as specified in MIL-STD-883 (see 3.1 herein) for class M or MIL-I-38535 for classes Q and V. Finish letter "X" shall not be marked on the microcircuit or its packaging. The "X" designation is for use in specifications when lead finishes A, B, and C are considered acceptable and interchangeable without preference.

Storage temperature range (T_STG) . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to +150°C Supply voltage range 1/2/3/. . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V dc to +6.5 V dc Input voltage range (V_IN) 1/2/3/4/ . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V dc to 6.5 V dc Instantaneous maximum current single pin limit (applies to all pins) 1/2/3/5/ . . . . . 25 mA Power dissipation (P_D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690 mW Operating maximum current digital input disruptive current range V_SS −0.3 ≤ V_IN ≤ V_DD +0.3 5/6/7/ . . . . . . . . . . . . . . . . . . . . . . . . . − to +500 µA Thermal resistance, junction-to-case (θ_JC) Case Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10°C/W Case Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10°C/W Lead temperature range (soldering, 5 seconds) . . . . . . . . . . . . . . . . . . . . 270°C

Case operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to +125°C Supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.50 V dc ≤ V_CC ≤ 5.50 V dc PLL reference frequency range (f_REF) . . . . . . . . . . . . . . . . . . . . . . . . . 25 to 50 KHz System frequency 8/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.78 MHz On-chip PLL system frequency (f_SYS) . . . . . . . . . . . . . . . . . . . . . . . . . 0.131 ≤ f_SYS ≤ 16.78 MHz External clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.78 MHz PLL lock time (t_LPLL) 9/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ms Limp mode clock frequency (f_LIMP): 10/ SYNCR × bit = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . f_SYSmax/2 MHz SYNCR × bit = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . f_SYSmax MHz CLKOUT stability (C_TAB) 11/12/ Short term . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1.0 to +1.0% Long term . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to +0.5%

Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) . . . . . . . . . . . . . . . . . . . . 13/ percent

intended Use: