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IPC-TM-650 2.6.3.5

Bare Board Cleanliness by Surface Insulation Resistance

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Organization: IPC
Publication Date: 1 January 2004
Status: active
Page Count: 4
scope:

This test method is used to characterize the cleanliness of printed wiring board fabrication processes by determining the degradation of electrical insulation resistance under conditions of high temperature and humidity.

This test method examines the cleanliness of a test substrate prior to solder mask application, after solder mask application, and after any final metalization and/or surface finish operation (e.g., HASL or OSP), and may be used to demonstrate the cleanliness of internal layers of a mulitilayer board prior to lamination.

Document History

IPC-TM-650 2.6.3.5
January 1, 2004
Bare Board Cleanliness by Surface Insulation Resistance
This test method is used to characterize the cleanliness of printed wiring board fabrication processes by determining the degradation of electrical insulation resistance under conditions of high...

References

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