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NPFC - MIL-M-38510/754

MICROCIRCUITS, DIGITAL, ADVANCED CMOS, LATCHES, MONOLITHIC SILICON

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Organization: NPFC
Publication Date: 29 June 1992
Status: inactive
Page Count: 27
scope:

This specification covers the detail requirements for monolithic silicon, advanced, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance (RHA) are provided and are reflected in the complete Part or Identifying Number (PIN). The PIN shall be formulated in accordance with MIL-M-38510.

The device types shall be as follows:

Device type Circuit 01 To be included at a later date 02 To be included at a later date 03 Octal transparent latch with three-state outputs 04 Octal transparent latch with inverted three-state outputs 05 Octal D-type latch with inverted three-state outputs 06 Octal D-type latch with three-state outputs

The device class shall be the product assurance level as defined in MIL-M-38510.

The case outlines shall be designated as follows:

Outline letter Case outline (see MIL-M-38510, appendix C) R D-8 (20-lead, 1.060" × .310" × .200"), dual-in-line package S F-9 (20-lead, .540" × .300" × .100"), flat package 2 C-2 (20 terminal, .358" × .358" × .100"), square chip carrier package

Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Rome Laboratory (RL/ERDS), Griffiss AFB, NY 13441-5700, by using the Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.

Supply voltage range (VCC) - - - - - - - - - - - - - - - −0.5 V dc to +6.0 V dc DC input voltage range (VIN) - - - - - - - - - - - - - - −0.5 V dc to VCC + 0.5 V dc DC output voltage range (VOUT) - - - - - - - - - - - - - −0.5 V dc to VCC + 0.5 V dc Clamp diode current (IIK, IOK) - - - - - - - - - - - - - ±20 mA DC output current (IOUT) - - - - - - - - - - - - - - - - ±50 mA DC VCC or GND current (ICC, IGND) - - - - - - - - - - - ±100 mA Storage temperature range (TSTG) - - - - - - - - - - - - −65°C to +150°C Maximum power dissipation (PD) - - - - - - - - - - - - - 500 mW Lead temperature (soldering, 10 seconds) - - - - - - - - +300°C Thermal resistance, junction-to-case (ΘJC) - - - - - - - See MIL-M-38510, appendix C Junction temperature (TJ) - - - - - - - - - - - - - - - +175°C Case operating temperature (TC) - - - - - - - - - - - - −55°C to +125°C

Supply voltage range (VCC) - - - - - - - - - - - - - - - +3.0 V dc to +5.5 V dc Input voltage range (VIN) - - - - - - - - - - - - - - - +0.0 V dc to VCC Output voltage range (VOUT) - - - - - - - - - - - - - - +0.0 V dc to VCC Case operating temperature range (TC) - - - - - - - - - −55°C to +125°C Input low (VIL) maximum voltage- - - - - - - - - - - - - 0.90 V dc at VCC = 3.0 V dc 1.35 V dc at VCC = 4.5 V dc 1.65 V dc at VCC = 5.5 V dc Input high (VIH) minimum voltage - - - - - - - - - - - - 2.10 V dc at VCC = 3.0 V dc 3.15 V dc at VCC = 4.5 V dc 3.85 V dc at VCC = 5.5 V dc Input rise and fall rate (tr,tf) maximum: VCC = 3.6 V, VCC = 5.5 V - - - - - - - - - - - - - - 8 ns/V Minimum setup time, Dn to LE (ts): Device type: 03 04 05 and 06 Unit VCC = 3.0 V dc; TC = +25°C, −55°C - - - - - - - - 5.5 2.0 2.0 ns TC = +125°C - - - - - - - - - - - 6.5 2.0 2.0 ns VCC = 4.5 V dc; TC = +25°C, −55°C - - - - - - - - 4.0 2.0 2.0 ns TC = +125°C - - - - - - - - - - - 5.0 2.0 2.0 ns Minimum hold time, Dn to LE (th): Device type: 03 04 05 and 06 Unit VCC = 3.0 V dc; TC = +25°C, −55°C - - - - - - - - 1.0 5.0 5.0 ns TC = +125°C - - - - - - - - - - - 1.0 5.0 5.0 ns VCC = 4.5 V dc; TC = +25°C; −55°C - - - - - - - - 1.0 3.0 3.0 ns TC = +125°C - - - - - - - - - - - 1.0 3.0 3.0 ns Minimum LE pulse width, (tw): Device type: 03 04 05 and 06 Unit VCC = 3.0 V dc; TC = +25°C; −55°C - - - - - - - - 5.5 10.0 10.0 ns TC = +125°C - - - - - - - - - - - 6.5 10.0 10.0 ns VCC = 4.5 V dc; TC = +25°C; −55°C - - - - - - - - 5.0 6.0 6.0 ns TC = +125°C - - - - - - - - - - - 5.0 6.0 6.0 ns

intended Use:

Microcircuits conforming to this specification are intended for original equipment design application and logistic support of existing equipment.

Document History

August 21, 2019
Microcircuits, Digital, Advanced CMOS, Latches, Monolithic Silicon
A description is not available for this item.
September 30, 2014
Microcircuits, Digital, Advanced CMOS, Latches, Monolithic Silicon
A description is not available for this item.
December 16, 2009
Microcircuits, Digital, Advanced CMOS, Latches, Monolithic Silicon
This specification covers the detail requirements for monolithic silicon, advanced CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation...
March 8, 2005
MICROCIRCUITS, DIGITAL, ADVANCED CMOS, LATCHES, MONOLITHIC SILICON
This specification covers the detail requirements for monolithic silicon, advanced CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation...
July 25, 2002
MICROCIRCUITS, DIGITAL, ADVANCED CMOS, LATCHES, MONOLITHIC SILICON
A description is not available for this item.
August 9, 1996
MICROCIRCUITS, DIGITAL, ADVANCED CMOS, LATCHES, MONOLITHIC SILICON
A description is not available for this item.
December 29, 1992
MICROCIRCUITS, DIGITAL, ADVANCED CMOS, LATCHES, MONOLITHIC SILICON
A description is not available for this item.
MIL-M-38510/754
June 29, 1992
MICROCIRCUITS, DIGITAL, ADVANCED CMOS, LATCHES, MONOLITHIC SILICON
This specification covers the detail requirements for monolithic silicon, advanced, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and...
April 13, 1990
MICROCIRCUITS, DIGITAL, ADVANCED CMOS, LATCHES, MONOLITHIC SILICON
A description is not available for this item.

References

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