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JEDEC JESD 35

Procedure for the Wafer-Level Testing of Thin Dielectrics

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Organization: JEDEC
Publication Date: 1 April 2001
Status: active
Page Count: 47
scope:

The revised JESD35 is intended for use in the MOS Integrated Circuit manufacturing industry. It describes procedures developed for estimating the overall integrity and reliability of thin gate oxides. Three basic test procedures are described, the Voltage-Ramp (V-Ramp), the Current-Ramp (J-Ramp) and the new Constant Current (Bounded J-Ramp) test. Each test is designed for simplicity, speed and ease of use. The standard has been updated to include breakdown criteria that are more robust in detecting breakdown in thinner gate oxides that may not experience hard thermal breakdown.

Document History

JEDEC JESD 35
April 1, 2001
Procedure for the Wafer-Level Testing of Thin Dielectrics
The revised JESD35 is intended for use in the MOS Integrated Circuit manufacturing industry. It describes procedures developed for estimating the overall integrity and reliability of thin gate...
January 1, 1992
Procedure for the Wafer-Level Testing of Thin Dielectrics
A description is not available for this item.

References

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