JEDEC JESD 82-6
Definition of the SSTV32852 2.5-V 24-BIT TO 48-Bit SSTL_2 Registered Buffer for 1U Stacked DDR DIMM Applications
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| Organization: | JEDEC |
| Publication Date: | 1 November 2002 |
| Status: | inactive |
| Page Count: | 14 |
Document History
January 1, 2023
Definition of the SSTV32852 2.5-V 24-Bit to 48-Bit SSTL_2 Registered Buffer for 1U Stacked DDR DIMM Applications
This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the 32852 24-bit to 48-bit SSTL_2 registered buffer for stacked DDR...
November 1, 2004
Definition of the SSTV32852 2.5-V 24-Bit to 48-Bit SSTL_2 Registered Buffer for 1U Stacked DDR DIMM Applications
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV32852 24-bit to 48-bit SSTL_2 registered buffer for stacked...
JEDEC JESD 82-6
November 1, 2002
Definition of the SSTV32852 2.5-V 24-BIT TO 48-Bit SSTL_2 Registered Buffer for 1U Stacked DDR DIMM Applications
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