JEDEC - JESD82-6A.01
Definition of the SSTV32852 2.5-V 24-Bit to 48-Bit SSTL_2 Registered Buffer for 1U Stacked DDR DIMM Applications
active, Most Current
| Organization: | JEDEC |
| Publication Date: | 1 January 2023 |
| Status: | active |
| Page Count: | 18 |
scope:
This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the 32852 24-bit to 48-bit SSTL_2 registered buffer for stacked DDR DIMM applications.
The purpose is to provide a standard for the 32852 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.
NOTE The designation 32852 refers to the part designation of a series of commercial logic parts common in the industry. This number is normally preceded by a series of manufacturer specific characters to make up a complete part designation.
Document History
JESD82-6A.01
January 1, 2023
Definition of the SSTV32852 2.5-V 24-Bit to 48-Bit SSTL_2 Registered Buffer for 1U Stacked DDR DIMM Applications
This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the 32852 24-bit to 48-bit SSTL_2 registered buffer for stacked DDR...
November 1, 2004
Definition of the SSTV32852 2.5-V 24-Bit to 48-Bit SSTL_2 Registered Buffer for 1U Stacked DDR DIMM Applications
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV32852 24-bit to 48-bit SSTL_2 registered buffer for stacked...
November 1, 2002
Definition of the SSTV32852 2.5-V 24-BIT TO 48-Bit SSTL_2 Registered Buffer for 1U Stacked DDR DIMM Applications
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