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DLA - SMD-5962-95651

MICROCIRCUIT, DIGITAL, RADIATION HARDENED ADVANCED CMOS, QUAD 2-INPUT AND GATE, MONOLITHIC SILICON

inactive
Organization: DLA
Publication Date: 29 December 1995
Status: inactive
Page Count: 15
scope:

This drawing forms a part of a one part - one part number documentation system (see 6.6 herein). Two product assurance classes consisting of military high reliability (device classes Q and M) and space application (device class V), and a choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). Device class M microcircuits represent non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883, "Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices". When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.

The PIN shall be as shown in the following example:

Device class M RHA marked devices shall meet the MIL-I-38535 appendix A specified RHA levels and shall be marked with the appropriate RHA designator. Device classes Q and V RHA marked devices shall meet the MIL-I-38535 specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.

The device type(s) shall identify the circuit function as follows:

Device type Generic number Circuit function 01 ACS08 Radiation hardened, SOS, advanced CMOS, quad 2-input AND gate

The device class designator shall be a single letter identifying the product assurance level as follows:

Device class Device requirements documentation M Vendor self-certification to the requirements for non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883 Q or V Certification and qualification to MIL-I-38535

The case outline(s) shall be as designated in MIL-STD-1835 and as follows:

Outline letter Descriptive designator Terminals Package style C CDIP2-T14 14 Dual-in-line X CDFP3-F14 14 Flat pack

The lead finish shall be as specified in MIL-STD-883 (see 3.1 herein) for class M or MIL-I-38535 for classes Q and V. Finish letter "X" shall not be marked on the microcircuit or its packaging. The "X" designation is for use in specifications when lead finishes A, B, and C are considered acceptable and interchangeable without preference.

Supply voltage range (VCC) . . . . . . . . . . . . . . . . . . -0.5 V dc to +6.0 V dc DC input voltage range (VIN) . . . . . . . . . . . . . . . . . -0.5 V dc to VCC + 0.5 V dc DC output voltage range (VOUT) . . . . . . . . . . . . . . . . -0.5 V dc to VCC + 0.5 V dc DC input current, any one input (IIN) . . . . . . . . . . . . ±10 mA DC output current, any one output (IOUT) . . . . . . . . . . . ±50 mA Storage temperature range (TSTG) . . . . . . . . . . . . . . . -65°C to +150°C Lead temperature (soldering, 10 seconds) . . . . . . . . . . . +265°C Thermal resistance, junction-to-case (ΘJC): Case outline C . . . . . . . . . . . . . . . . . . . . . . . 24°C/W Case outline X . . . . . . . . . . . . . . . . . . . . . . . 30°C/W Thermal resistance, junction-to-ambient (ΘJA): Case outline C . . . . . . . . . . . . . . . . . . . . . . . 74°C/W Case outline X . . . . . . . . . . . . . . . . . . . . . . . 116°C/W Junction temperature (TJ) . . . . . . . . . . . . . . . . . . +175°C Maximum package power dissipation at TA = +125°C (PD): 4/ Case outline C . . . . . . . . . . . . . . . . . . . . . . . 0.68 W Case outline X . . . . . . . . . . . . . . . . . . . . . . . 0.43 W

Supply voltage range (VCC) . . . . . . . . . . . . . . . . . . . . . . . +4.5 V dc to +5.5 V dc Input voltage range (VIN) . . . . . . . . . . . . . . . . . . . . . . . +0.0 V dc to VCC Output voltage range (VOUT). . . . . . . . . . . . . . . . . . . . . . . +0.0 v dc to VCC Maximum low level input voltage (VIL) . . . . . . . . . . . . . . . . . 30% of VCC Minimum high level input voltage (VIH) . . . . . . . . . . . . . . . . . 70% of VCC Case operating temperature range (TC) . . . . . . . . . . . . . . . . . -55°C to +125°C Maximum input rise and fall time at VCC = 4.5 V (tr, tf) . . . . . . . . 10 ns/V Radiation features: Total dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 〉 3 x 105 Rads (Si) Single event phenomenon (SEP) effective linear energy threshold (LET) no upsets (see 4.4.4.4) . . . . . . . 〉 100 MeV/(cm2/mg) 5/ Dose rate upset (20 ns pulse) . . . . . . . . . . . . . . . . . . . . 〉 1 x 1011 Rads (Si)/s 5/ Latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None 5/ Dose rate survivability . . . . . . . . . . . . . . . . . . . . . . . 〉 1 x 1012 Rads (Si)/s 5/

Document History

July 17, 2000
MICROCIRCUIT, DIGITAL, RADIATION HARDENED ADVANCED CMOS, QUAD 2-INPUT AND GATE, MONOLITHIC SILICON
This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes...
April 13, 1999
MICROCIRCUIT, DIGITAL, RADIATION HARDENED ADVANCED CMOS, QUAD 2-INPUT AND GATE, MONOLITHIC SILICON
A description is not available for this item.
October 22, 1997
MICROCIRCUIT, DIGITAL, RADIATION HARDENED ADVANCED CMOS, QUAD 2-INPUT AND GATE, MONOLITHIC SILICON
A description is not available for this item.
SMD-5962-95651
December 29, 1995
MICROCIRCUIT, DIGITAL, RADIATION HARDENED ADVANCED CMOS, QUAD 2-INPUT AND GATE, MONOLITHIC SILICON
This drawing forms a part of a one part - one part number documentation system (see 6.6 herein). Two product assurance classes consisting of military high reliability (device classes Q and M) and...

References

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