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JEDEC JEP 119

A Procedure for Performing SWEAT

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Organization: JEDEC
Publication Date: 1 August 2003
Status: active
Page Count: 32
scope:

This document describes an algorithm for performing the Standard Wafer Level Electromigration Accelerated Test (SWEAT) method with computer controlled instrumentation. The algorithm requires a separate iterative technique (not provided) to calculate the force current for a given target time to failure.

This document does not specify what test structure to use with this procedure. However, users of this algorithm report its effectiveness on both straight-lines and via-terminated test structures. Some teststructures design features are provided in JESD87 and in ASTM 1259M - 96.

Document History

JEDEC JEP 119
August 1, 2003
A Procedure for Performing SWEAT
This document describes an algorithm for performing the Standard Wafer Level Electromigration Accelerated Test (SWEAT) method with computer controlled instrumentation. The algorithm requires a...
JEDEC JEP 119
August 1, 2003
A Procedure for Performing SWEAT
This document describes an algorithm for performing the Standard Wafer Level Electromigration Accelerated Test (SWEAT) method with computer controlled instrumentation. The algorithm requires a...
JEDEC JEP 119
January 1, 1994
Procedure for Executing SWEAT
A description is not available for this item.

References

This document references:
JEDEC JESD 33 - Standard Method for Measuring and Using the Temperature Coefficient of Resistance to Determine the Temperature of a Metallization Line
Published by JEDEC on February 1, 2004
This newly revised test method provides a procedure for measuring the temperature coefficient of resistance, TCR(T), of thin-film metallizations used in microelectronic circuits and devices....
This document references:
JEDEC JESD 37 - LOGNORMAL ANALYSIS OF UNCENSORED DATA AND OF SINGLY RIGHT-CENSORED DATA UTILIZING THE PERSSON AND ROOTZEN METHOD
Published by JEDEC on August 1, 2017
Intent This standard enables the user to estimate the parameters of a two-parameter lognormal distribution from complete or singly right-censored independent data samples. Specifically, this standard...
This document references:
JEDEC JESD 61 - Isothermal Electromigration Test Procedure
Published by JEDEC on October 1, 2007
This standard describes an algorithm for the execution of the isothermal test, using computer-controlled instrumentation. The primary use of this test is for the monitoring of microelectronic...
This document references:
JEDEC JESD 63 - Standard Method for Calculating the Electromigration Model Parameters for Current Density and Temperature
Published by JEDEC on February 1, 1998
This method provides procedures to calculate sample estimates and their confidence intervals for the electromigration model parameters of current density and temperature. The model parameter for...
This document references:
JEDEC JESD 87 - Standard Test Structures for Reliability Assessment of AICu Metallizations with Barrier Materials
Published by JEDEC on July 1, 2001
This document describes design of test structures needed to assess the reliability of aluminum-copper, refractory metal barrier interconnect systems. This includes any metal interconnect system where...
This document is referenced by:
IEC TS 62686-1 - Process management for avionics – Electronic components for aerospace, defence and high performance (ADHP) applications – Part 1: General requirements for high reliability integrated circuits and discrete semiconductors
Published by IEC on April 1, 2020
This part of IEC 62686, which is a Technical Specification, defines the minimum requirements for general purpose "off the shelf" COTS (commercial off-the-shelf) integrated circuits and discrete...
This document is referenced by:
BS DD IEC TS 62239 - Process management for avionics Preparation of an electronic components management plan
Published by BSI on August 14, 2003
A description is not available for this item.
This document is referenced by:
BS PD IEC TS 62686-1 - Process management for avionics - Electronic components for aerospace, defence and high performance (ADHP) applications Part 1: General requirements for high reliability integrated circuits and discrete semiconductors
Published by BSI on April 30, 2020
A description is not available for this item.
This document is referenced by:
IEC 62239-1 - Process management for avionics – Management plan – Part 1: Preparation and maintenance of an electronic components management plan
Published by IEC on September 1, 2018
This part of IEC 62239 defines the requirements for developing an electronic components management plan (ECMP) to guarantee to customers that all of the electronic components in the equipment of the...
This document is referenced by:
JEDEC JEP 122 - Failure Mechanisms and Models for Semiconductor Devices
Published by JEDEC on September 1, 2016
This publication provides a list of failure mechanisms and their associated activation energies or acceleration factors that may be used in making system failure rate estimations when the only...
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