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JEDEC JEP 156

Chip-Package Interaction Understanding, Identification, and Evaluation

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Organization: JEDEC
Publication Date: 1 March 2018
Status: active
Page Count: 24
scope:

This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products. CPI test structures may not be a prerequisite for device qualification dependent on the device technology; however, if the effect of CPI on a device technology placed in a specific packaging scheme is not known, there could be reliability concerns for that component that are not evident with standard component level test structures. Therefore, it is recommended that CPI test structures are used and the associated testing and failure analysis be performed to determine if there are any adverse effects on that component due to packaging. Chip sizes and packages should be used that are representative of the product family to allow investigation of failure mechanisms for those products.

NOTE This publication covers only interaction between the semiconductor package stresses and the semiconductor device. Interactions between the assembled component and a second level assembly are not covered. See JEP 150 for information regarding assembled component reliability. Interactions resulting from package interconnect electromigration are also not covered. See JEP 154 regarding Package interconnect electromigration. . See JEP158 for the effects on chip reliability due to through-silicon vias (TSVs).

NOTE CPI tests should be performed in addition to process and package qualification typically performed on new products. These reliability stress tests have been found capable of stimulating and precipitating failures in components in an accelerated manner, but these tests should not be used indiscriminately. Each qualification should be examined for:

a) Any potential new and unique failure mechanism

b) Any situations where these tests/conditions may induce invalid or overstress failures.

In either case the set of reliability requirements, tests and/or conditions should be appropriately modified to properly include the new failure mechanisms and modes.

This document does not relieve the supplier of the responsibility to meet internal or customer specified qualification programs.

Document History

JEDEC JEP 156
March 1, 2018
Chip-Package Interaction Understanding, Identification, and Evaluation
This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as...
March 1, 2009
Chip-Package Interaction Understanding, Identification and Evaluation
This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as...

References

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