Generic Requirements for Surface Mount Design and Land Pattern Standard
|Publication Date:||1 June 2010|
This document provides information on land pattern geometries used for the surface attachment of electronic components. The intent of the information presented herein is to provide the appropriate size, shape and tolerance of surface mount land patterns to insure sufficient area for the appropriate solder fillet to meet the requirements of IPC/EIA J-STD-001, and also to allow for inspection, testing, and rework of those solder joints.
Although, in many instances, the land pattern geometries can be different based on the type of soldering used to attach the electronic part, wherever possible, land patterns are defined with consideration to the attachment process being used. Designers can use the information contained herein to establish standard configurations not only for manual designs but also for computer-aided design systems. Whether parts are mounted on one or both sides of the board, subjected to wave, reflow, or other type of soldering, the land pattern and part dimensions should be optimized to insure proper solder joint and inspection criteria.
Land patterns are dimensionally defined and are a part of the printed board circuitry geometry, as they are subject to the producibility levels and tolerances associated with plating, etching, assembly or other conditions. The producibility aspects also pertain to the use of solder mask and the registration required between the solder mask and the conductor patterns.
Note 1: The dimensions used for component descriptions have been extracted from standards developed by industrial and/or standards bodies. Designers should refer to these standards for additional or specific component package dimensions.
Note 2: For a comprehensive description of the given printed board and for achieving the best possible solder joints to the devices assembled, the whole set of design elements includes, beside the land pattern definition:
• Solder paste stencil.
• Clearance between adjacent components.
• Clearance between bottom of component and PCB surface, if relevant.
• Keepout areas, if relevant.
• Suitable rules for adhesive applications.
The whole of design elements is commonly defined as ''mounting conditions.'' This standard defines land patterns and includes recommendations for clearances between adjacent components and for other design elements.
Note 3: Elements of the mounting conditions, particularly the courtyard, given in this standard are related to the reflow soldering process. Adjustments for wave or other soldering processes, if applicable, have to be carried out by the user. This may also be relevant when solder alloys other than eutectic tin lead solders are used.
Note 4: This standard assumes that the land pattern follows the principle that, even under worst case conditions, the overlap of the component termination and the corresponding soldering land will be complete.
Note 5: Heat dissipation aspects have not been taken into account in this standard. Greater mass may require slower process speed to allow heat transfer.
Note 6: Heavier components (greater weight per land) require larger lands; thus, adding additional land pattern surface will increase surface area of molten solder to enhance capabilities of extra weight. In some cases the lands shown in the standard may not be large enough; in these cases, considering additional measures may be necessary.
Note 7: The land form may be rectangular with straight or rounded corners. In the latter case the area of the smallest circumscribed rectangle shall be equal to that of one with straight corners.
This standard identifies the generic physical design principles involved in the creation of land patterns for surface mount components, and is supplemented by a shareware IPC-7351 Land Pattern viewer that provides, through the use of a graphical user interface, the individual component dimensions and corresponding land pattern recommendations based upon families of components. The IPC-7351 Land Pattern Viewer is provided on CD-ROM as part of the IPC-7351. Updates to land pattern dimensions, including patterns for new component families, can be found on the IPC website (www.ipc.org) under ''PCB Tools and Calculators.'' See Appendix C for more information on the IPC-7351 Land Pattern Viewer.
Component and Land Pattern Family Structure
The IPC-7351 provides the following number designation within the IPC-7350 series for each major family of surface mount components to indicate similarities in solder joint engineering goals:
IPC-7352 - Discrete Components
IPC-7353 - Gullwing Leaded Components, Two Sides
IPC-7354 - J-Leaded Components, Two Sides
IPC-7355 - Gullwing Leaded Components, Four Sides
IPC-7356 - J-Leaded Components, Four Sides
IPC-7357 - Post (DIP) Leads, Two Sides
IPC-7358 - Area Array Components (BGA, FBGA, CGA)
IPC-7359 - No Lead Components (QFN, SON, LCC)
Three general end-product classes have been established to reflect progressive increases in sophistication, functional performance requirements and testing/inspection frequency. It should be recognized that there may be an overlap of equipment between classes.
The end product user has the responsibility for determining the ''Use Category'' or ''Class'' to which the product belongs. The contract between user and supplier shall specify the ''Class'' required and indicate any exceptions or additional requirements to the parameters, where appropriate.
Class 1 General Electronic Products - Includes consumer products, some computer and computer peripherals, and hardware suitable for applications where the major requirement is function of the completed assembly.
Class 2 Dedicated Service Electronic - Products Includes communications equipment, sophisticated business machines, and instruments where high performance and extended life is required, and for which uninterrupted service is desired but not mandatory. Typically the end-use environment would not cause failures.
Class 3 High Reliability Electronic Products - Includes all equipment where continued performance or performance-on-deman
The IPC-7351 land patterns have the capability of accommodating all three performance classifications.
When appropriate this standard will provide three design producibility levels of features, tolerances, measurements, assembly, testing of completion or verification of the manufacturing process that reflect progressive increases in sophistication of tooling, materials or processing and, therefore progressive increases in fabrication cost. These levels are:
Level A General Design Producibility - Preferred
Level B Moderate Design Producibility - Standard
Level C High Design Producibility - Reduced
The producibility levels are not to be interpreted as a design requirement, but a method of communicating the degree of difficulty of a feature between design and fabrication/assembly
Classification of producibility levels should not be confused with density levels of land pattern geometries described in 1.4.
Land Pattern Determination
This standard discusses two methods of providing information on land patterns.
1. Exact details based on industry component specifications, board manufacturing and component placement accuracy capabilities. These land patterns are restricted to a specific component, and have an identifying IPC-7351 land pattern name.
2. Equations can be used to alter the given information to achieve a more robust solder connection, when used in particular situations where the equipment for placement or attachment are more or less precise than the assumptions made when determining the land pattern details (see 3.1.2).
Three land pattern geometry variations are supplied for each of the device families; maximum land protrusion (Density Level A), median land protrusion (Density Level B) and minimum land protrusion (Density Level C). Before adapting the minimum land pattern variations the user should consider product qualification testing based on the conditions shown in Table 3-15.
Density Level A: Maximum (Most) Land Protrusion - For low-density product applications, the 'maximum' land pattern condition has been developed to accommodate wave or flow solder of leadless chip devices and leaded gull-wing devices. The geometry furnished for these devices, as well as inward and ''J''-formed lead contact device families, may provide a wider process window for reflow solder processes as well.
Density Level B: Median (Nominal) Land Protrusion - Products with a moderate level of component density may consider adapting the 'median' land pattern geometry. The median land patterns furnished for all device families will provide a robust solder attachment condition for reflow solder processes and should provide a condition suitable for wave or reflow soldering of leadless chip and leaded gull-wing type devices.
Density Level C: Minimum (Least) Land Protrusion - High component density typical of portable and hand-held product applications may consider the 'minimum' land pattern geometry variation. Selection of the minimum land pattern geometry may not be suitable for all product use categories. The use of classes of performance (1, 2, and 3) is combined with that of component density levels (A, B, and C) in explaining the condition of an electronic assembly. As an example, combining the description as Levels 1A or 3B or 2C, would indicate the different combinations of performance and component density to aid in understanding the environment and the manufacturing requirements of a particular assembly.
Note: It is the responsibility of the user to verify the SMT land patterns used for achieving an undisturbed mounting process, including testing and an ensured reliability for the product stress conditions in use. In addition the size and shape of the proposed land pattern may vary according to the solder resist aperture, the size of the land pattern extension (dog bone), the via within the extension, or if the via is in the land pattern itself.
Terms and Definitions
Terms and definitions used herein are in accordance with IPC-T-50 except as otherwise specified. Note: Any definition denoted with an asterisk (*) is a reprint of the term defined in IPC-T-50.
*Assembly - A number of parts, subassemblies or combinations thereof joined together. (Note: This term can be used in conjunction with other terms listed herein, e.g., ''Printed Board Assembly.'')
Assembly, Double-Sided - Packaging and interconnecting structure with components mounted on both the primary and secondary sides.
Assembly, Multilayer Printed Circuit (wiring) - Multilayer printed circuit or printed wiring board on which separately manufactured components and parts have been added.
Assembly, Packaging and Interconnecting (P&IA) - Generic term for an assembly that has electronic components mounted on either one or both sides of a packaging and interconnecting structure.
Assembly, Printed Board - An assembly of several printed circuit assemblies or printed wiring assemblies, or both.
Assembly, Printed Circuit (wiring) - A printed circuit or printed wiring board on which separately manufactured components and parts have been added.
Assembly, Single-Sided - Packaging and interconnecting structure with components mounted only on the primary side.
*Base Material - The insulating material upon which a conductive pattern may be formed. (The base material may be rigid or flexible, or both. It may be a dielectric or insulated metal sheet.)
*Basic Dimension - A numerical value used to describe the theoretical exact location of a feature or hole. (It is the basis from which permissible variations are established by tolerance on other dimensions in notes or by feature control symbols.)
*Blind Via - A via extending only to one surface of a printed board.
*Buried Via - A via that does not extend to the surface of a printed board.
*Castellation - A recessed metalized feature on the edge of a leadless chip carrier that is used to interconnect conducting surface or planes within or on the chip carrier.
*Chip Carrier - A low-profile, usually square, surface-mount component semiconductor package whose die cavity or die mounting area is a large fraction of the package size and whose external connections are usually on all four sides of the package. (It may be leaded or leadless.)
*Chip-On-Board (COB) - A printed board assembly technology that places unpackaged semiconductor dice and interconnects them by wire bonding or similar attachment techniques. Silicon area density is usually less than that of the printed board.
*Coefficient of Thermal Expansion (CTE) - The linear dimensional change of a material per unit change in temperature. (See also ''Thermal Expansion Mismatch.'')
*Component - An individual part or combination of parts that, when together, perform a design function(s). (See also ''Discrete Component.'')
*Component Mounting Site - The location on a Package Interconnect (P&I) structure that consists of a land pattern and conductor fan-out to additional lands for testing or vias that are associated with the mounting of a single component.
*Conductive Pattern - The configuration or design of the conductive material on a base material. (This includes conductors, lands, vias, heatsinks and passive components when these are an integral part of the printed board manufacturing process.)
*Conductor - A single conductive path in a conductive pattern.
*Constraining Core - A supporting plane that is internal to a packaging and interconnecting structure.
Courtyard - The smallest rectangular area that provides a minimum electrical and mechanical clearance (courtyard excess) around the combined component body and land pattern boundaries.
Courtyard Excess - The area between the rectangle circumscribing the land pattern and the component, and the outer boundary of the courtyard. The courtyard excess may be different in the x- and y-direction.
Courtyard Manufacturing Zone - The area that provides a minimum electrical and mechanical clearance (courtyard excess) around the combined component body and land pattern boundries.
*Dual-Inline Package (DIP) - A basically-rectangula
*Fine-Pitch Technology (FPT) - A surface-mount assembly technology with component terminations on less than 0.625 mm [0.025 in] centers.
*Fiducial (Mark) - A printed board artwork feature(s) that is created in the same process as the conductive pattern and that provides a common measurable point for component mounting with respect to a land pattern or land patterns.
*Flat Pack - A rectangular component package that has a row of leads extending from each of the longer sides of its body that are parallel to the base of its body.
*Footprint - See ''Land Pattern.''
*Grid - An orthogonal network of two sets of parallel equidistant lines that is used for locating points on a printed board.
*Integrated Circuit (IC) - A combination of inseparable associated circuit elements that are formed in place and interconnected on or within a single base material to perform a particular electrical function.
*Jumper wire - A discrete electrical connection that is part of the original design and is used to bridge portions of the basic conductive pattern formed on a printed board.
*Land - A portion of a conductive pattern usually used for the connection and/or attachment of components.
*Land Pattern - A combination of lands that is used for the mounting, interconnection and testing of a particular component.
*Leadless Chip Carrier - A chip carrier whose external connections consist of metallized terminations that are an integral part of the component body. (See also ''Leaded Chip Carrier.'')
Leaded Chip Carrier - A chip carrier whose external connections consist of leads that are around and down the side of the package. (See also ''Leadless Chip Carrier.'')
*Master Drawing - A control document that shows the dimensional limits or grid locations that are applicable to any and all parts of a product to be fabricated, including the arrangement of conductors and nonconductive patterns or elements; the size, type, and location of holes; and all other necessary information.
Mixed Component-Mounting Technology - A component mounting technology that uses both through-hole and surface-mounting technologies on the same packaging and interconnecting structure.
*Module - A separable unit in a packaging scheme.
Nominal Dimension - A dimension that is between the maximum and minimum size of a feature. (The tolerance on a nominal dimension gives the limits of variation of a feature size.)
*Packaging and Interconnecting Structure (P&IS) - The general term for a completely processed combination of base materials, supporting planes or constraining cores, and interconnection wiring that are used for the purpose of mounting and interconnecting components.
*Plated-Through Hole (PTH) - A hole with plating on its walls that makes an electrical connection between conductive patterns on internal layers, external layer, or both, of a printed board.
*Primary Side - The side of a packaging and interconnecting structure that is so defined on the master drawing. (It is usually the side that contains the most complex or the most number of components.)
*Printed Board (PB) - The general term for completely processed printed circuit and printed wiring configurations. (This includes single-sided, double-sided and multilayer boards with rigid, flexible, and rigid-flex base materials.)
*Printed Wiring - A conductive pattern that provides point-to-point connections but not printed components in a predetermined arrangement on a common base. (See also ''Printed Circuit.'')
*Registration - The degree of conformity of the position of a pattern (or portion thereof), a hole, or other feature to its intended position on a product.
*Secondary Side - That side of a packaging and interconnecting structure that is opposite the primary side. (It is the same as the ''solder side'' on through-hole mounting technology.)
*Single-Inline Package (SIP) - A component package with one straight row of pins or wire leads.
Static Charge - An electrical charge that has accumulated or built up on the surface of a material
Static Electricity Control - A technique where materials and systems are employed to eliminate/discharge static electricity build-up by providing continuous discharge paths
*Supported Hole - A hole in a printed board that has its inside surfaces plated or otherwise reinforced.
*Supporting Plane - A planar structure that is a part of a packaging and interconnecting structure in order to provide mechanical support, thermomechanical constraint, thermal conduction and/or electrical characteristics. (It may be either internal or external to the packaging and interconnecting structure.) (See also ''Constraining Core.'')
*Surface Mount Technology (SMT) - The electrical connection of components to the surface of a conductive pattern that does not utilize component holes.
*Tented Via (Type I Via) - A via with a mask material (typically dry film) applied bridging over the via wherein no additional materials are in the hole. It may be applied to one side or both.
*Thermal Mismatch - The absolute difference between the thermal expansion of two components or materials. (See also ''Coefficient of Thermal Expansion (CTE).'')
*Through Connection - The electrical connection to connect conductor patterns on the front side through to the back side of a printed board. (See also ''Interfacial Connection. '')
*Through-Hole Technology (THT) - The electrical connection of components to a conductive pattern by the use of component holes.
*Tooling Feature - A physical feature that is used exclusively to position a printed board or panel during a fabrication, assembly or testing process. (See also ''Locating Edge,'' ''Locating Edge Marker,'' ''Locating Notch,'' ''Locating Slot,'' and ''Tooling Hole.'')
*Via - A plated-through hole that is used as an interlayer connection, but in which there is no intention to insert a component lead or other reinforcing material. (See also ''Blind Via'' and ''Buried Via.'')