Process management for avionics – Aerospace and defence electronic systems containing lead-free solder – Part 3: Performance testing for systems containing lead-free solder and finishes
|Publication Date:||1 July 2011|
|ICS Code (Production. Production management):||03.100.50|
|ICS Code (Electronic components in general):||31.020|
|ICS Code (Aerospace electric equipment and systems):||49.060|
This PAS defines for circuit card assemblies (CCA)
- a default method for those companies that require a pre-defined approach and
- a protocol for those companies that wish to develop their own test methods.
The default method (Section 4 of the PAS) is intended for use by electronic equipment manufacturers, repair facilities, or programs that, for a variety of reasons, may be unable to develop methods specific to their own products and applications. It is to be used when little or no other information is available to define, conduct, and interpret results from reliability, qualification, or other tests for electronic equipment containing Lead-free (Pb-free) solder. The default method is intended to be conservative, i.e., it is biased toward minimizing the risk to users of AHP electronic equipment.
The protocol (Section 5 of the PAS) is intended for use by manufacturers or repair facilities that have the necessary resources to design and conduct reliability, qualification, or process development tests that are specific to their products, their operating conditions, and their applications. Users of the protocol will have the necessary knowledge, experience, and data to customize their own methods for designing, conducting, and interpreting results from the data. Key to developing a protocol is a firm understanding of all material properties for the Lead-free (Pb-free) material in question as well as knowledge of package- and board-level attributes as described in Section 4.1.1. As an example, research has shown that the mechanisms for creep can be different between Tin-Lead and Tin-Silver-Copper (SAC) solders. Understanding these mechanisms is key to determining critical test parameters such as dwell time for thermal cycling. The protocol portion of this document provides guidance on performing sufficient characterization of new materials in order to accurately define test parameters.
Use of the protocol is encouraged, since it is likely to yield more accurate results, and to be less expensive than the default method. Reference  provides a comprehensive overview of those technical considerations necessary in implementing a test protocol.
This PAS addresses the evaluation of failure mechanisms, thru
performance testing, expected in electronic products containing
Lead-free (Pb-free) solder. One failure mode, fatigue-failure thru
the solder-joint, is considered a primary failure mode in AHP
electronics and can be understood in terms of physics of failure
and life-projections. Understanding all of the potential failure
modes caused by Lead-free (Pb-free) solder of AHP electronics is a
critical element in defining early field-failures/relia
When properly used, the methods or protocol defined in this PAS may be used along with the processes documented in compliance to Reference , to satisfy, at least in part, the reliability requirements of References  and .
This PAS may be used for products in all stages of the transition to Lead-free (Pb-free) solder, including:
• Products that have been designed and qualified with traditional Tin-Lead electronic components, materials, and assembly processes, and are being re-qualified with use of Lead-free (Pb-free) components
• Products with Tin-Lead designs transitioning to Lead-free (Pb-free) solder; and
• Products newly-designed with Lead-free (Pb-free) solder.
For programs that were designed with Tin-Lead solder, and are currently not using any Leadfree (Pb-free) solder, the traditional methods may be used. It is important, however, for those programs to have processes in place to maintain the Tin-Lead configuration including those outsourced or manufactured by subcontractors.
With respect to products as mentioned above, the methods presented in this document are intended to be applied at the level of assembly at which soldering occurs, i.e., circuit-card assembly level.