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DLA - SMD-5962-90965 REV A

MICROCIRCUIT, MEMORY, DIGITAL, CMOS, FIELD PROGRAMMABLE GATE ARRAY, 2,000 GATES, MONOLITHIC SILICON

inactive
Organization: DLA
Publication Date: 23 June 1993
Status: inactive
Page Count: 19
scope:

This drawing forms a part of a one part - one part number documentation system (see 6.6 herein). Two product assurance classes consisting of military high reliability (device classes B, Q, and M) and space application (device classes S and V), and a choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). Device class M microcircuits represent non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883, "Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices". When available, a choice of radiation hardness assurance (RHA) levels are reflected in the PIN.

The PIN shall be as shown in the following example:

Device classes M, B, and S RHA marked devices shall meet the MIL-M-38510 specified RHA levels and shall be marked with the appropriate RHA designator. Device classes Q and V RHA marked devices shall meet the MIL-I-38535 specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.

The device type(s) shall identify the circuit function as follows:

Device type Generic number Circuit function Bin speed 01 1020 2000 gate, field programmable gate array 186 ns 02 1020-1 2000 gate, field programmable gate array 158 ns

The device class designator shall be a single letter identifying the product assurance level (see 6.6 herein) as follows:

Device class Device requirements documentation M Vendor self-certification to the requirements for non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883 B or S Certification and qualification to MIL-M-38510 Q or V Certification and qualification to MIL-I-38535

The case outline(s) shall be as designated in MIL-STD-1835 and as follows:

Outline letter Descriptive designator Terminals Package style X CQCC2 - J44 44 J-lead chip carrier Y CQCC2 - J68 68 J-lead chip carrier Z CQCC2 - J84 84 J-lead chip carrier U CMGA15 - PN 84 Pin grid array 1/ T CQCC1 - F84 84 Unformed lead chip carrier

The lead finish shall be as specified in MIL-M-38510 for classes M, B, and S or MIL-I-38535 for classes Q and V. Finish letter "X" shall not be marked on the microcircuit or its packaging. The "X" designation is for use in specifications when lead finishes A, B, and C are considered acceptable and interchangeable without preference.

DC supply voltage range (VDD)- - - - - - - - - - - - - - −0.5 V dc to +7.0 V dc Input voltage range (VI) - - - - - - - - - - - - - - - - −0.5 V dc to VDD + 0.5 V dc Output voltage range (VO)- - - - - - - - - - - - - - - - −0.5 V dc to VDD + 0.5 V dc Input clamp current (IIC)- - - - - - - - - - - - - - - - ±20 mA Output clamp current (IOC) - - - - - - - - - - - - - - - ±20 mA Continuous output current IO)- - - - - - - - - - - - - - ±25 mA Storage temperature range (TSTG) - - - - - - - - - - - - −65°C to +150°C Lead temperature (soldering, 10 seconds) - - - - - - - - 300°C Thermal resistance, junction-to-case (θJC) - - - - - - - See MIL-STD-1835 Maximum junction temperature (TJ) - - - - - - - - - - - +175°C

Supply voltage (VDD) - - - - - - - - - - - - - - - - - - +4.5 V dc to +5.5 V dc Case operating temperature range (TC)- - - - - - - - - - −55°C to +125°C

Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012)- - - - - - XX percent 3/

intended Use:

Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes.

Microcircuits... View More

Document History

SMD 5962-90965
November 26, 2018
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, FIELD PROGRAMMABLE GATE ARRAY, 2,000 GATES, MONOLITHIC SILICON
This drawing documents two product assurance class levels consisting of high reliability (device class Q and M) and space application (device class V). A choice of case outlines and lead finishes are...
SMD 5962-90965
May 1, 2018
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, FIELD PROGRAMMABLE GATE ARRAY, 2,000 GATES, MONOLITHIC SILICON
This drawing documents two product assurance class levels consisting of high reliability (device class Q and M) and space application (device class V). A choice of case outlines and lead finishes are...
SMD 5962-90965
April 2, 2018
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, FIELD PROGRAMMABLE GATE ARRAY, 2,000 GATES, MONOLITHIC SILICON
This drawing documents two product assurance class levels consisting of high reliability (device class Q and M) and space application (device class V). A choice of case outlines and lead finishes are...
SMD 5962-90965
November 7, 2011
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, FIELD PROGRAMMABLE GATE ARRAY, 2,000 GATES, MONOLITHIC SILICON
This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes...
SMD-5962-90965 REV G
May 13, 2005
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, FIELD PROGRAMMABLE GATE ARRAY, 2,000 GATES, MONOLITHIC SILICON
This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes...
SMD-5962-90965 REV F
March 8, 2004
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, FIELD PROGRAMMABLE GATE ARRAY, 2,000 GATES, MONOLITHIC SILICON
A description is not available for this item.
SMD-5962-90965 REV E
September 21, 1998
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, FIELD PROGRAMMABLE GATE ARRAY, 2,000 GATES, MONOLITHIC SILICON
This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes...
SMD-5962-90965 REV D
July 10, 1998
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, FIELD PROGRAMMABLE GATE ARRAY, 2,000 GATES, MONOLITHIC SILICON
This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes...
SMD-5962-90965 REV C
April 6, 1998
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, FIELD PROGRAMMABLE GATE ARRAY, 2,000 GATES, MONOLITHIC SILICON
This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes...
SMD-5962-90965 REV B
June 30, 1994
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, FIELD PROGRAMMABLE GATE ARRAY, 2,000 GATES, MONOLITHIC SILICON
This drawing forms a part of a one part - one part number documentation system (see 6.6 herein). Two product assurance classes consisting of military high reliability (device classes Q and M) and...
SMD-5962-90965 REV A
June 23, 1993
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, FIELD PROGRAMMABLE GATE ARRAY, 2,000 GATES, MONOLITHIC SILICON
This drawing forms a part of a one part - one part number documentation system (see 6.6 herein). Two product assurance classes consisting of military high reliability (device classes B, Q, and M) and...
SMD-5962-90965
June 23, 1992
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, FIELD PROGRAMMABLE GATE ARRAY, 2,000 GATES, MONOLITHIC SILICON
A description is not available for this item.
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References

This document references:
MIL-STD-1835 - Electronic Component Case Outlines
Published by NPFC on September 21, 2009
This standard establishes and maintains a compilation of electronic component case outlines and should be useful to all levels of manufacturing that culminate in the production of reliable and...
This document references:
ASTM F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices
Published by ASTM on October 1, 2011
This guide defines the requirements and procedures for testing integrated circuits and other devices for the effects of single event phenomena (SEP) induced by irradiation with heavy ions having an...
This document references:
JEDEC JESD 78 - IC Latch-Up Test
Published by JEDEC on April 1, 2016
This standard covers the I-test and Vsupply overvoltage latch-up testing of integrated circuits. The purpose of this standard is to establish a method for determining IC latch-up characteristics and...
This document references:
MIL-HDBK-103 - LIST OF STANDARD MICROCIRCUIT DRAWINGS
Published by NPFC on March 8, 2021
Purpose. The Standard Microcircuit Drawing Program (SMDP) is directly under the auspices of the DoD Parts Management Program (PMP). The PMP is implemented by MIL-HDBK-512, "Parts Management." The PMP...
This document references:
MIL-HDBK-780D VALID NOTICE 1 - Standard Microcircuit Drawings
Published by DLA on December 28, 2021
A description is not available for this item.
This document references:
MIL-PRF-38535M - INTEGRATED CIRCUITS (MICROCIRCUITS) MANUFACTURING, GENERAL SPECIFICATION FOR
Published by DLA on November 1, 2022
Scope. This specification establishes the general performance requirements for integrated circuits or microcircuits and the quality and reliability assurance requirements, which are to be met for...
This document references:
MIL-STD-883 - TEST METHOD STANDARD MICROCIRCUITS
Published by NPFC on September 16, 2019
Purpose. This standard establishes uniform methods, controls, and procedures for testing microelectronic devices suitable for use within Military and Aerospace electronic systems including basic...
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