scope:

This drawing documents three product assurance class levels consisting of space application (device class V), high reliability (device classes M and Q), and nontraditional performance environment (device class N). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. For device class N, the user is cautioned to assure that the device is appropriate for the application environment.

The PIN shall be as shown in the following example:

Device classes N, Q, and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.

The device type(s) shall identify the circuit function as follows:

Device type Generic number Circuit function Access time 01 XQ4036XL-3 36000 gate programmable array 3.0 ns

The device class designator shall be a single letter identifying the product assurance level as follows:

Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A N Certification and qualification to MIL-PRF-38535 with a non-traditional performance environment encapsulated in plastic Q or V Certification and qualification to MIL-PRF-38535

The case outline(s) are as designated in MIL-STD-1835, JEDEC Publication 95, and as follows:

Outline letter Descriptive designator Terminals Package style X CMGA36-P411 411 Pin grid array package y See figure 1 228 Quad flat package Z See figure 1 228 Quad flat package U LBGA-B-352 352 Ball grid array with four rows on each side (plastic) (JEDEC MO-192-BAR-2) T PQFP-G-240 240 Quad flat package (JEDEC MS-029-GA) with heat sink molded in the package (plastic)

The lead finish is as specified in MIL-PRF-38535 for device classes N, Q, and V or MIL-PRF-38535, appendix A for device class M.

Supply voltage range to ground potential (V_CC) ------- −0.5 V dc to +4.0 V dc DC input voltage range ( V_IN ) ----------------------- −0.5 V to 5.5V Voltage applied to three-state output(V_TS) ----------- −0.5 V to 5.5V Lead temperature (soldering, 10 seconds) -------------------- +260EC Power dissipation (PD ) ------------------------------------- 2.0 W Thermal resistance, junction-to-case (1 _JC): Case outline X --------------------------------------------- See MIL-STD-1835 Case outlines Y, Z ----------------------------------------- 20EC/W 3/ Case outlines U -------------------------------------------- 0.8EC/W 3/ Case outlines T -------------------------------------------- 1.5EC/W 3/ Junction temperature (T_J for ceramic packages -------- +150EC 4/ Junction temperature (T_J for plastic packages -------- +125EC 4/ Storage temperature range ----------------------------------- −65EC to + 150EC

Supply voltage relative to ground(V_CC) --------------- +3.0 V dc minimum to +3.6 V dc maximum Input high voltage ( V_IH) ---------------------------- 50% of V_CC to 5.5 V Input low voltage (V_IL) ------------------------------ OV to 30% of V_CC Maximum input signal transition time (t_IN) ----------- 250 ns Case operating temperature range (T_C) ---------------- −55EC to + 125EC Junction operating temperature range (T_J) ------------- −55EC to + 125EC for Plastic packages

Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) ------------------------ 99.9 percent

intended Use: