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DLA - SMD-5962-93124

MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 2K X 9 PARALLEL FIFO, MONOLITHIC SILICON

inactive
Organization: DLA
Publication Date: 29 October 1993
Status: inactive
Page Count: 30
scope:

This drawing forms a part of a one part - one part number documentation system (see 6.6 herein). Two product assurance classes consisting of military high reliability (device classes Q and M) and space application (device class V), and a choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). Device class M microcircuits represent non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883, "Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices". When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.

The PIN shall be as shown in the following example:

Device class M RHA marked devices shall meet the MIL-I-38535 appendix A specified RHA levels and shall be marked with the appropriate RHA designator. Device classes Q and V RHA marked devices shall meet the MIL-I-38535 specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.

The device type(s) shall identify the circuit function as follows:

Device type Generic number 1/ Circuit function Access time 01 7C453 2K × 9 Cascadable Clocked FIFO 30 ns 02 7C453 2K × 9 Cascadable Clocked FIFO 20 ns 03 7C453 2K × 9 Clocked FIFO 14 ns

The device class designator shall be a single letter identifying the product assurance level as follows:

Device class Device requirements documentation M Vendor self-certification to the requirements for non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883 Q or V Certification and qualification to MIL-I-38535

The case outline(s) shall be as designated in MIL-STD-1835 and as follows:

Outline letter Descriptive designator Terminals Package style X See figure 1 32 Dual-in-line Package Y CQCC1-N32 32 Rectangular leadless chip carrier

The lead finish shall be as specified in MIL-STD-883 (see 3.1 herein) for class M or MIL-I-38535 for classes Q and V. Finish letter "X" shall not be marked on the microcircuit or its packaging. The "X" designation is for use in specifications when lead finishes A, B, and C are considered acceptable and interchangeable without preference.

Supply voltage range to ground potential (VCC) - - - - - - −0.5 V dc to +7.0 V dc DC voltage applied to the outputs in the high Z state - - −0.5 V dc to +7.0 V dc DC input voltage - - - - - - - - - - - - - - - - - - - - −3.0 V dc to +7.0 V dc Maximum power dissipation - - - - - - - - - - - - - - - - 0.825 W Lead temperature (soldering, 10 seconds) - - - - - - - - +260°C Thermal resistance, junction-to-case (ΘJC): Case X - - - - - - - - - - - - - - - - - - - - - - - - 11°C/W Case Y - - - - - - - - - - - - - - - - - - - - - - - - See MIL-STD-1835 Junction temperature (TJ) - - - - - - - - - - - - - - - - +175°C Storage temperature range - - - - - - - - - - - - - - - - −65°C to +150°C Temperature under bias - - - - - - - - - - - - - - - - - −55°C to +125°C

Supply voltage (VCC)- - - - - - - - - - - - - - - - - - - +4.5 V dc minimum to +5.5 V dc maximum Ground voltage (GND) - - - - - - - - - - - - - - - - - - 0 V dc Input high voltage (VIH) - - - - - - - - - - - - - - - - 2.2 V dc minimum Input low voltage (VIL) - - - - - - - - - - - - - - - - 0.8 V dc maximum Case operating temperature range (TC) - - - - - - - - - - −55°C to +125°C

Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) . . . . . . 3/ percent

intended Use:

Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes.

Document History

October 20, 2017
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 2K X 9 PARALLEL FIFO, MONOLITHIC SILICON
This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes...
January 20, 2011
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 2K X 9 PARALLEL FIFO, MONOLITHIC SILICON
This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes...
May 2, 2005
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 2K X 9 PARALLEL FIFO, MONOLITHIC SILICON
This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes...
May 4, 2001
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 2K X 9 PARALLEL FIFO, MONOLITHIC SILICON
A description is not available for this item.
SMD-5962-93124
October 29, 1993
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 2K X 9 PARALLEL FIFO, MONOLITHIC SILICON
This drawing forms a part of a one part - one part number documentation system (see 6.6 herein). Two product assurance classes consisting of military high reliability (device classes Q and M) and...

References

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