scope:

This document describes the design and assembly challenges for implementing Ball Grid Array (BGA) and Fine Pitch BGA (FBGA) technology. The effect of BGA and FBGA on current technology and component types is also addressed. The focus on the information contained herein is on critical inspection, repair, and reliability issues associated with BGAs.

Purpose

The target audiences for this document are managers, design and process engineers, and operators and technicians who deal with the electronic assembly, inspection, and repair processes. The intent is to provide useful and practical information to those who are using BGAs and those who are considering BGA implementation.

Selection Criteria (Determination of Package Style and Assembly Processes)

Every electronic system consists of various parts: interfaces, electronic storage media, and the printed board assembly. Typically, the complexity of these systems is reflected in both the type of components used and their interconnecting structure. The more complex the components, as judged by the amount of input/output terminals they possess, the more complex is the interconnecting substrate.

Cost and performance drivers have resulted in increased component density, and a greater number of components attached to a single assembly, while the available mounting real estate has shrunk. In addition, the number of functions per device has increased and this is accommodated by using increased I/O count and reduced contact pitch. Reduced contact pitch represents challenges for both assemblers and bare board manufacturers. Assemblers encounter handling, coplanarity and alignment problems.

The board manufacturers must deal with land size issues, solder mask resolution and electrical test problems.

Based on industry predictions one would believe that all component packages have over 200 I/Os and are increasing in I/O count. Actually, components with the highest usage have I/O counts in the 16 to 64 I/O range. Over 50% of all components fall into this category, while only 5% of all components used have over 208 I/Os, which may be the threshold for determining the cross-over point between peripheral leaded component style packages and array type formats.

Many peripherally leaded, lower I/O count devices, such as memory and logic devices, are being converted to area array packaging formats as either BGAs or Fine Pitch BGAs.

Although the percentage of high I/O components used on an electronic assembly is small, they play a big part in driving the industry infrastructure for both bare board and assembly manufacturing. These high I/O components determine the process for bare board imaging, etching, testing and surface finishing. They determine the materials used for fabrication and drive assembly process improvements in a similar manner.

The electronics industry has evolved from using through-hole assembly technology in which the component leads went into the printed board substrate and were either soldered to the bottom side of the board or into a plated-through hole. Surface Mounting Technology (SMT) has advanced to a stage where the majority of electronic components manufactured today are only available in SMT form.

Manufacturing products with SMT in any significant volume requires automation. For low volume, a manually operated machine or a single placement machine may be sufficient. High volume SMT manufacturing requires special solder paste deposition systems, multiple and various placement machines, in-line solder reflow systems and cleaning systems.

The heart of surface mount manufacturing is the machine that places the components onto the printed board land areas prior to soldering. Unlike through-hole (TH) insertion machines, surface mount placement machines are usually capable of placing many different component types. As design densities have increased, new SMT package styles have evolved. Examples are Fine Pitch Technology (FPT), Ultra Fine Pitch Technology (UFPT), and Array Surface Mount (ASM). This latter category consists of the many families of ball or column grid arrays and the chip scale packages (CSP) and Fine Pitch BGAs (FBGA). These parts are all capable of being placed by machines provided that the equipment has the required positioning accuracy.

Increased device complexity has been a primary driving factor for SMT. In order to minimize the component package size, component lead spacing has decreased (e.g., 1.27 mm to 0.65 mm). Further increases in semiconductor integration requiring more than 196 I/Os can drive packages to even closer perimeter lead spacing, such as 0.5 mm, 0.4 mm, 0.3 mm, and 0.25 mm. However, the array package format has become the favorite for high I/O count devices. Area array component package styles have a pitch that originally was much larger than the equivalent peripherally leaded device, however that lead format is now also seeing reductions in pitch configurations.

Ball and column grid arrays were standardized in 1992 with 1.5, 1.27 and 1.0 mm pitch. Fine Pitch BGA array packages standards have established pitches of 1.0 mm, 0.8, 0.75, 0.65, and 0.5 mm. There are some implementations of FBGAs where the pitch has been reduced to 0.4 mm, and future components are being evaluated with 0.3 and 0.25 mm pitch configurations.

The via pattern for the board requires much tighter feature control as the pitch for BGA, FBGA and CSP becomes smaller. There is a question as to how many lead pitches are required between 1.0 mm and 0.5 mm. Some indicate that a 60% rule is of value where the ball diameter is 60% of the pitch. This results in a 0.5 mm ball diameter for a 0.8 mm pitch. FBGA would use a 0.4 mm ball diameter for a 0.65 mm pitch. On the other hand, some feel that it would be better to standardize a 0.3 mm diameter ball for all FBGA packages.

Standardization of a single ball size would facilitate many characteristics. The motive is to accommodate conductor routing on the interconnecting substrate and help standardize socket pin contact design.

Area array packaging has the intrinsic value of being able to make coherent designs. This is exemplified on the right side of Figure 1-1, where a single pitch might be depopulated to meet the requirements of the design. The trend illustrated on the left side of Figure 1-1 forces the creation of many different test sockets. Interconnection of the part IOs is affected both by ball pitch and ball diameter. The standard ball diameter as specified by the US JEDEC JC11 Committee alleviates pressure on the substrate design.

The selection process for an electronic assembly should attempt to minimize the variation in component package types and the I/O pitch condition. The large I/O count devices and problems with assembly of finer pitch peripheral packages has caused rethinking of the packaging style vs. the assembly complexity relationship, and the printed board interconnection and surface characteristics.

The concern in using these very complex parts relates to board design and assembly issues. Assembly is concerned about attaching all the leads to the mounting structure without bridging (shorts) or missing solder joints (opens). Design is concerned with interconnecting all the leads and having sufficient room for routing conductors.

Array packages permit a variety of ball configurations, e.g., staggered positions or partially populated parts, to provide the room required for adequate conductor routing. With a common base array pitch significant advantages can be gained in terms of providing a coherent standard for all of the elements of the electronic manufacturing infrastructure for components, sockets, substrates and test systems (see Figure 1-2).

The role of the interconnecting substrate continues to grow performing circuit functions beyond simply providing interconnection wiring. In addition, organic copper clad laminates have been targeted to replace the ceramic interconnecting structure inside large components, such as Plastic Ball Grid Arrays (BGAs) or Array formatted SMDs as shown in Figure 1-3. Thus organic substrates must meet the thermal and moisture-resistance profile for the single chip or multi device BGA configuration parts, as well as the performance requirements defined by the present standards.

The interconnecting and mounting structure will require greater precision in the placement and definition of the conductors and in the dielectric properties of the material.

Moreover, the substrate used will likely require that the interconnecting structure already contain materials necessary for attachment of the components (e.g., solder bumps, palladium coated lands, conductive adhesive).

With more of the circuit customization going into silicon and with the component package size increasing, the printed board design will need to change. The higher I/O demand will require multilayer or high-density interconnection (microvia) designs to support the required wiring and to provide escape routing from the internal connections of array component patterns to the printed board. Both sides of the printed board may be required to place all the components required by the design. There will also be an increased demand on the printed board to handle the required power dissipation.

Using high I/O components like BGAs and fine pitch BGAs creates the challenge of routing all the required signal, power, and ground I/O balls to the PWB without increasing PWB complexity and therefore cost. Thoughtful package pin assignments and the package configuration considerations (pitch, ball size, ball count, and depopulation) can go a long way in making the board routing easier.

Two interconnection signal layers can be sufficient for BGA package escape, even when the BGA has very high ball counts, providing the pin assignments are properly planned and the escape routing is carefully designed. Table 1-1 indicates the number of ''escapes'' possible on two layers of circuitry versus the array size and the number of conductors between lands/vias. It should be noted that as the number of I/O increases, the ability to escape diminishes and thus more layers may be required. At first glance, Table 1-1 might appear to indicate that two routing layers are insufficient to escape any array greater than 16 x 16 (256 balls). In reality, a significant number of the balls will be used for power and ground connections and therefore do not need ''escape'' routing. They can be directly connected to the appropriate plane through the dogbone via attached to the land. That being said, poor placement of the signal or power/ground balls can ''waste'' available routing channels and significantly reduce the total number of signal I/Os that can be routed out in a given number of layers.

Placing signal pin assignments on the outer rows of an array package, and using the inner balls for power and ground will facilitate escape routing. However, the corner balls of large array packages are more suspectible to mechanical failure, and therefore it may be better to use these for redundant ground connections.The number of rows of signal I/O that can be routed out will depend on the desired number of conductor routing layers in the printed board and the number of conductors that can be routed between lands and vias.

Figure 1-4 shows examples of conductor and space widths that will fit between adjacent lands with various pitches and land diameters. Note that as the ball pitch decreases, the conductor width and spacing for a given number of conductors per channel also decreases, and it becomes more difficult and costly to produce the board. Using 150 µm conductors and spaces is quite cost effective, but printed board cost begins to increase significantly for 100 µm conductors and spaces.

Using an organic interconnecting substrate to mount the bare die within a plastic BGA requires that the mounting lands on the substrate match the bonding lands on the die.

The bonding lands are typically positioned for wire bonding, since this is the most popular technique. Thermally conductive adhesive is one of the methods used to attach the back of the die to the substrate. Depending on the number of I/O and the lead pitch, multilayer substrate fabrication techniques may be used to translate a peripheral bonding land die, to an area array matrix of bumps, balls, or columns (see Figure 1-5).

The transition of chip bonding lands that are in an array format permits the mounting of the die in flip chip configurations. In this instance, the die is mounted opposite to that which is wire-bonded and the bumps of the die come into direct contact with the substrate being used to convert the die pattern to the BGA pattern. This creates new challenges for the routing requirements for the organic high-density microcircuit board manufacturer. In addition, underfill is usually required to maintain some consistency between the CTE of the chip and the CTE of the organic multilayer board (see Figure 1-6).

To accommodate a flip chip with area array I/O lands at 0.25 mm pitch, the BGA package substrate will need bonding lands at 0.25 mm pitch on the top side, and solder balls at 1.27 or 1.00 mm pitch on the bottom side. These opposing sets of lands must be connected by the BGA package substrate (High-Density Microcircuit Board) wiring and interlevel vias or PTHs. It may be necessary to have one or more interconnecting lines between two adjacent bonding lands on the topside of the BGA substrate. This is done in order to access multiple rows of the interior I/O lands for connection to the vias or PTHs for eventual connection to the solder balls on the bottom side. Very aggressive layout rules must be used, even when designing with surface redistribution layers (see Figure 1-7).

For high performance chips with 1700 pin requirements, a BGA with very dense wiring layers is required. The body size of such a BGA would be 50 mm. In all probability, there would be depopulated solder balls in the middle of the BGA. Regarding pitch, such a BGA substrate would require a 1.00 mm via and solder ball pitch, which would accommodate a ball density of 100 I/O per square centimeter.

Technology Comparison

The principles used to mount a single chip into an organic carrier package can also be used to connect several chips together. This technique is referred to as a multichip module-laminate (MCM-L) or a multichip package (MCP) or the new name assigned to complex module assemblies known as multi Device Subassembly (MDS). In all the variations that are being developed the one governing condition is the use of the area array format. Thus, ball size and pitch will continue to be the process governing factor for individual components or those that encompass more than one semiconductor die. Table 1-2 shows some examples of an attempt to establish a definition for Multichip modules housing more than one die. Figure 1-8 is an example of one such product using the area array concepts for interconnection.

Possible other descriptive attributes include substrate technology (e.g., -C for ceramic, -L for laminate, -D for deposited, - W for wafer, -S for silicon) & interconnection technology (e.g., -WB for wire bond, -FC for flip chip, - MX for mixed).

Microprocessors typically have between 40 - 60% of their I/O dedicated to power and ground. As an example, a package might have a total of 1300 - 1400 I/O where the signal count is between 600 and 700 I/O. Applications Specific ICs (ASICs) may differ in that I/O apportionment. The signal I/O escape wiring, and their interconnection to other high I/O packages, will also require very high density printed boards (HDBs). As the number of I/O on a chip increases further, the body size of the single chip package may become unacceptably large, and could require reassessment of the overall package solution, including considering multichip module packaging or Application Specific Module Packaging as an alternative.

The signal I/O count for high performance BGAs is about 2.5 times that commonly required for BGAs used in hand held products. The interconnection density requirement is linearly proportional to the number of signal I/O per package, and inversely proportional to the center-to-center pitch between adjacent packages. A 2.5X increase in signal I/O from 500 to 1300 pins per package at the same package-to-package pitch will require a PWB with a 2.5X increase in its wiring density, and a proportional increase in the density of the interlevel vias or PTHs. This may require a reduction in the PTH/via pitch, and an increase in the number of signal layers in the PWB.