JEDEC JEP 149
Application Thermal Derating Methodologies
|Publication Date:||1 January 2021|
This publication applies to the application of integrated circuits and their associated packages in end use designs. It summarizes the methodology of thermal derating and the suitability of such methodologies.
NOTE This publication advocates the use of derating, but leaves the amount of derating up to the user. This should vary depending on many application requirements including reliability, criticality, functional performance needs, etc. Also note that mechanical related mechanisms (such as vibration, shock, etc.) may not be suitable for derating per the methodology described here.