JEDEC JESD 51-4
THERMAL TEST CHIP GUIDELINE (WIRE BOND AND FLIP CHIP)
|Publication Date:||1 June 2019|
The purpose of this document is to provide a design guideline for thermal test chips used for integrated circuit (IC) and transistor package thermal characterization and investigations. The intent of this guideline is to minimize the differences in data gathered due to nonstandard test chips and to provide a well-defined reference for thermal investigations.
The thermal test chips described in this document will apply to single and multiple chip devices. These are designed using standard semiconductor wafer fabrication processes and can be used with a wide variety of industry standard packages. These test chips can operate in a static mode in which constant power is continuously supplied to the device while monitoring the temperature through the measurement of a Temperature Sensitive Parameter (TSP). They can also operate in a transient mode in which the power supply and the TSP are monitored as a function of time (t). This guideline covers test chips meant to be both wire bonded or flip chip bumped to the package external contacts.