This document references:
JEDEC JESD 252 - Serial Flash Reset Signaling Protocol
Published by JEDEC
on
October 1, 2018
This standard specifies the signaling protocol for hardware resetting a Serial Flash device. The protocol can be used in the absence of or in addition to a dedicated RESET# pin on the device.
This document references:
JEDEC JESD 216 - Serial Flash Discoverable Parameters (SFDP)
Published by JEDEC
on
November 1, 2018
The SFDP standard defines the structure of the SFDP database within the memory device and methods used to read its data. The JEDEC-defined header with Parameter ID FF00h and the related Basic...
This document references:
JEDEC JESD 100 - Terms, Definitions, and Letter Symbols for Microcomputers, Microprocessors, and Memory Integrated Circuits
Published by JEDEC
on
December 1, 2002
A revised reference for technical writers and educators, manufacturers, buyers and users of microprocessors, microcomputers, mircocontrollers, memory ICs, and other complex devices. The terms and...
This document references:
JEDEC JESD 216 - Serial Flash Discoverable Parameters (SFDP)
Published by JEDEC
on
November 1, 2018
The SFDP standard defines the structure of the SFDP database within the memory device and methods used to read its data. The JEDEC-defined header with Parameter ID FF00h and the related Basic...
This document references:
JEDEC JESD 252 - Serial Flash Reset Signaling Protocol
Published by JEDEC
on
October 1, 2018
This standard specifies the signaling protocol for hardware resetting a Serial Flash device. The protocol can be used in the absence of or in addition to a dedicated RESET# pin on the device.
This document references:
JEDEC JESD 8-26 - 1.2 V HIGH‐SPEED LVCMOS (HS_LVCMOS) INTERFACE
Published by JEDEC
on
September 1, 2011
This standard defines the dc and ac input levels, output levels, and input overshoot and undershoot specifications for the 1.2 V High-speed LVCMOS (HS_LVCMOS) interface. The non-terminated interface...
This document is referenced by:
JESD261 - Serial NOR Security Hardware Abstraction Layer
Published by JEDEC
on
October 1, 2022
This standard provides a comprehensive definition of the NOR cryptographic security hardware abstraction layer (HAL). It also provides design guidelines and reference software to reduce design-in...
This document is referenced by:
JESD254 - Secure Serial Flash Bus Transactions
Published by JEDEC
on
December 1, 2022
This standard describes SPI bus transactions intended to support Secure Flash operation on a serial memory device. The on-chip SFDP database described in JESD216 has been revised to include details...