DLA - SMD-5962-92316 REV A
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 1MEG X 1 STATIC RANDOM ACCESS MEMORY (SRAM) WITH SEPARATE I/O, MONOLITHIC SILICON
| Organization: | DLA |
| Publication Date: | 5 June 1996 |
| Status: | inactive |
| Page Count: | 28 |
scope:
This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.
The PIN is as shown in the following example:
Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
The device type(s) identify the circuit function as follows:
Device type Generic number 1/ Circuit function Data retention Access time 01 1 MEG × 1 CMOS SRAM No 45 ns 02 1 MEG × 1 CMOS SRAM No 35 ns 03 1 MEG × 1 CMOS SRAM No 25 ns 04 1 MEG × 1 CMOS SRAM No 20 ns 05 1 MEG × 1 CMOS SRAM Yes 45 ns 06 1 MEG × 1 CMOS SRAM Yes 35 ns 07 1 MEG × 1 CHOS SRAM Yes 25 ns 08 1 MEG × 1 CMOS SRAM Yes 20 ns
The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535
The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter Descriptive designator Terminals Package style X See figure 1 32 dual-in-line Y See figure 1 32 rectangular leadless chip carrier Z See figure 1 32 flat pack U See figure 1 32 SOJ package T See figure 1 28 dual-in-line
The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M.
Voltage on any input relative to VSS - - - - - - - - −0.5 V dc to +7.0 V dc Voltage applied to Q - - - - - - - - - - - - - - - - −0.5 V dc to +6.0 V dc Storage temperature range - - - - - - - - - - - - - - −65°C to +150°C Maximum power dissipation (PD) - - - - - - - - - - - 1.0 W Lead temperature (soldering, 10 seconds) - - - - - - +260°C Thermal resistance, junction-to-case (ΘJC): Cases X and T - - - - - - - - - - - - - - - - - - - 5°C/W Case Y - - - - - - - - - - - - - - - - - - - - - - 4°C/W Cases U and Z - - - - - - - - - - - - - - - - - - - 6°C/W Junction temperature (TJ) - - - - - - - - - - - - - - +150°C 3/
Supply voltage range (VCC) - - - - - - - - - - - - - 4.5 V dc to 5.5 V dc Supply voltage (VSS) - - - - - - - - - - - - - - - - 0 V Input high voltage range (VIH) - - - - - - - - - - - 2.2 V dc to +6.0 V dc Input low voltage range (VIL) - - - - - - - - - - - - −0.5 V dc to +0.8 V dc 4/ Case operating temperature range (TC) - - - - - - - - −55°C to +125°C
Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) . . . . . . 5/ percent
intended Use:
Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes.
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