JEDEC JESD 241
Procedure for Wafer-Level DC Characterization of Bias Temperature Instabilities
|Publication Date:||1 December 2015|
The scope of this document is to provide a minimum common protocol for foundries and fabless customers to compare the dc BTI induced mean VT shift at an agreed End of Life (EOL) of a MOSFET transistor with a channel width, Wdes (Wdes ≥ Wmin - See Annex B) and length Ldes of a manufacturable CMOS process and technology. The BTI comparison is proposed at an assumed worst dc use conditions (VDDmax, TJmax). The procedure applies to both Negative (VGS < 0) (NBTI) and Positive (VGS > 0) (PBTI) BTI conditions for both pMOSFET and nMOSFET transistors.
The proposed procedure consists of two parts:
1) BTI stress/test characterization methodology
A two-step stress/test waveform with VGS and VDS switching between a capacitor-like BTI stress with no channel conduction (VGS = VGSstr, VDS= VDSstr = 0) and a single drain current, ID, measurement in linear mode (VGS =VGStst, VDS = VDStst < VDsat). The VGStst is chosen to estimate the constant current VT (VT(ci)) in the linear region of the weakly inverted region of the device IV characteristics to mainly monitor the associated flatband voltage shift (charge accumulation in the gate dielectric stack). Measurement is accomplished with a selected measuring delay (1 μs ≤ Δ ≤ 2 ms) from stress to test bias conditions. The procedure to determine Δ is given in paragraph 6. As a reference, a procedure to determine ID shifts in linear or saturation mode and VT(ci) shift in saturation mode during dc BTI stressing is given in Annex A.
2) DC EOL VT shift estimation at worst VDDnom/T dc use conditions.
Estimation of dc VT shift at a given EOL is performed once a phenomenological BTI model is derived that is representative of the dc BTI sensitivity of the CMOS processes and/or technologies under evaluation. Section 7, describes this procedure and Annex C suggests a possible VGSstr/Tstr design of experiments to estimate the DC BTI model parameters.