DLA - SMD-5962-95600 REV C
MICROCIRCUITS, MEMORY, DIGITAL, 512K X 8 STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON
| Organization: | DLA |
| Publication Date: | 24 October 1997 |
| Status: | inactive |
| Page Count: | 32 |
scope:
This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.
The PIN is as shown in the following example:
Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
The device types identify the circuit function as follows:
Device type Generic number 1/ Circuit function Date retention Access time 01 512K × 8 CMOS SRAM No 45 ns 02 512K × 8 CMOS SRAM No 35 ns 03 512K × 8 CMOS SRAM No 25 ns 04 512K × 8 CMOS SRAM No 20 ns 05 512K × 8 CMOS SRAM Yes 45 ns 06 512K × 8 CMOS SRAM Yes 35 ns 07 512K × 8 CMOS SRAM Yes 25 ns 08 512K × 8 CMOS SRAM Yes 20 ns
The device class designator is a single letter identifying the product assurance level as follows:
Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535
The case outlines are as designated in MIL-STD-1835 and as follows:
Outline letter Descriptive designator Terminals Package style X GDIP1-T32 or CDIP2-T32 32 dual-in-line Y See figure 1 32 TSOP package Z See figure 1 32 leadless chip carrier U See figure 1 32 SOJ package T See figure 1 36 flat pack
Outline letter Descriptive designator Terminals Package style M See figure 1 36 SOJ package N See figure 1 36 leadless chip carrier 9 See figure 1 32 flat pack 8 See figure 1 36 SOJ package
The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M.
Voltage on any input relative to VSS ............... −0.5 V dc to +7.0 V dc
Storage temperature range ....................
Supply voltage range (VCC) ....................
Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) .............. 4/ percent
intended Use:
Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes.
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