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DLA - SMD-5962-95600 REV B

MICROCIRCUITS, MEMORY, DIGITAL, 512K X 8 STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON

inactive
Organization: DLA
Publication Date: 17 April 1997
Status: inactive
Page Count: 32
scope:

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.

The PIN is as shown in the following example:

Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.

The device types identify the circuit function as follows:

Device type Generic number 1/ Circuit function Data retention Access time 01 512K × 8 CMOS SRAM No 45 ns 02 512K × 8 CMOS SRAM No 35 ns 03 512K × 8 CMOS SRAM No 25 ns 04 512K × 8 CMOS SRAM No 20 ns 05 512K × 8 CMOS SRAM Yes 45 ns 06 512K × 8 CMOS SRAM Yes 35 ns 07 512K × 8 CMOS SRAM Yes 25 ns 08 512K × 8 CMOS SRAM Yes 20 ns

The device class designator is a single letter identifying the product assurance level as follows:

Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535

The case outlines are as designated in MIL-STD-1835 and as follows:

Outline letter Descriptive designator Terminals Package style X GDIP1-T32 or CDIP2-T32 32 dual-in-line Y See figure 1 32 TSOP package Z See figure 1 32 leadless chip carrier U See figure 1 32 SOJ package T See figure 1 36 flat pack

Outline letter Descriptive designator Terminals Package style M See figure 1 36 SOJ package N See figure 1 36 leadless chip carrier 9 See figure 1 32 flat pack 8 See figure 1 36 SOJ package

The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M.

Voltage on any input relative to VSS .............. −0.5 V dc to +7.0 V dc Storage temperature range ......................... −65°C to + 150°C Maximum power dissipation (PD) .................... 2.0 W Lead temperature (soldering, 10 seconds) .......... +260°C Thermal resistance, junction-to-case (ΘJC): Case X ........................................... See MIL-STD-1835 Case Y ........................................... 6° C/W Cases U, M, and 8 ................................ 11°C/W Case T ........................................... 10°C/W Cases Z and N .................................... 20°C/W Case 9 ........................................... 22°C/W Junction temperature (TJ) ......................... +150°C 2/ Output current .................................... 40 mA

Supply voltage range (VCC) .................... 4.5 V dc to 5.5 V dc Supply voltage (VSS) .......................... 0 V Input high voltage range (VIH) ................ 2.2 V dc to +6.0 V dc Input low voltage range (VIL) ................... −0.5 V dc to +0.8 V dc 3/ Case operating temperature range (TC) ........... −55°C to +125°C

Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) ...... 4/ percent

intended Use:

Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes.

Microcircuits... View More

Document History

March 30, 2022
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 512K X 8 STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON
Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. Replaceability....
January 24, 2020
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 512K X 8 STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON
Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q and M) and space application (device class V). A choice of case outlines and lead...
September 1, 2016
MICROCIRCUITS, MEMORY, DIGITAL, CMOS, 512K X 8 STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON
This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes...
January 22, 2009
MICROCIRCUITS, MEMORY, DIGITAL, CMOS, 512K X 8 STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON
This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes...
August 18, 2008
MICROCIRCUITS, MEMORY, DIGITAL, 512K x 8 STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON
This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes...
May 25, 2004
MICROCIRCUITS, MEMORY, DIGITAL, 512K X 8 STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON
A description is not available for this item.
February 12, 2002
MICROCIRCUITS, MEMORY, DIGITAL, 512K X 8 STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON
A description is not available for this item.
December 13, 2000
MICROCIRCUITS, MEMORY, DIGITAL, 512K X 8 STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON
Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. Microcircuits covered by...
November 22, 2000
MICROCIRCUITS, MEMORY, DIGITAL, 512K X 8 STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON
Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. Microcircuits covered by...
March 1, 2000
MICROCIRCUITS, MEMORY, DIGITAL, 512K X 8 STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON
Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. Microcircuits covered by...
October 24, 1997
MICROCIRCUITS, MEMORY, DIGITAL, 512K X 8 STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON
This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes...
SMD-5962-95600 REV B
April 17, 1997
MICROCIRCUITS, MEMORY, DIGITAL, 512K X 8 STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON
This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes...
November 27, 1996
MICROCIRCUITS, MEMORY, DIGITAL, 512K X 8 STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON
A description is not available for this item.
March 5, 1996
MICROCIRCUITS, MEMORY, DIGITAL, 512K X 8 STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON
This drawing forms a part of a one part - one part number documentation system (see 6.6 herein). Two product assurance classes consisting of military high reliability (device classes Q and M) and...

References

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