JEDEC JESD 8-15
Stub Series Terminated Logic for 1.8 V (SSTL_18)
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| Organization: | JEDEC |
| Publication Date: | 1 September 2003 |
| Status: | active |
| Page Count: | 22 |
scope:
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_18 logic switching range, nominally 0 V to 1.8 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. The VDD value is not specified in this standard; however VDD and VDDQ will have the same voltage level in many cases.
Document History
JEDEC JESD 8-15
September 1, 2003
Stub Series Terminated Logic for 1.8 V (SSTL_18)
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_18 logic switching range, nominally 0 V to 1.8 V. The standard may...
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